1. Field of the Related Art
The present invention relates to a multiport memory having a memory hold circuit and a plurality of write circuits, or a multiport memory having a memory hold circuit and a plurality of read circuits, on a semiconductor substrate. The present invention is especially preferable for the case where the memory hold circuit is a register file, an SRAM (Static random Access Memory), or the like.
2. Description of the Related Art
As a conventional multiport memory, there is known a memory which performs writing or reading not just once but a plurality of times per unit time so as to obtain a capability greater than a write/read capability per unit time which is determined with a bit width of each circuit. An example of such multiport memories is disclosed in “Media processor-oriented multiplex eight-port SRAM to operate at 350 MHz and a word length variable multiplier; Ichida, Sakurai et al., Shingaku Giho 96.04 (pages 59-60, FIG. 6)”.
In the above-mentioned conventional technique, the number of writing times and the number of reading times per unit time are common in all write circuits. Further, the number of writing times and the number of reading times per cycle are also common in all cycles.
However, in the case of providing a plurality of write circuits, write circuits required to have different write capabilities may be mixed as provided. When these write circuits are in common use and the number of writing times per cycle of all the write circuits is to be made common and fixed, the number of writing times per cycle is matched to the number of writing times per cycle of a circuit required to have the highest access capability. This is called rate controlling. The rate controlling necessitates an extra operation of each of the circuits. Consequently, as for a circuit having a low access capability, the circuit scale increases in an undesirable manner, and further the power consumption also increases.
Similarly, in the case of providing a plurality of read circuits, read circuits required to have different read capabilities may be mixed as provided. When these read circuits are in common use and the number of reading times per cycle of all the read circuits is to be made common and fixed, the number of reading times per cycle is matched to the number of reading times per cycle of a circuit required to have the highest access capability. This is also called rate controlling. The rate controlling necessitates an extra operation of each of the circuits. Consequently, as for a circuit having a low access capability, the circuit scale increases in an undesirable manner, and further the power consumption also increases.